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8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 1 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer g eneral d escription the ics8432i-101 is a general purpose, dual out- put differential-to-3.3v lvpecl high frequency synthesizer and a member of the hiperclocks? family of high performance clock solutions from ics. the ics8432i-101 has a selectable test_clk or clk, nclk inputs. the test_clk input accepts lvcmos or lvttl input levels and translates them to 3.3v lvpecl levels. the clk, nclk pair can accept most standard differential input levels. the vco operates at a frequency range of 250mhz to 700mhz. the vco frequency is programmed in steps equal to the value of the input differential or single ended reference frequency. the vco and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. the low phase noise characteristics of the ics8432i-101 makes it an ideal clock source for gigabit ethernet and sonet applications. b lock d iagram p in a ssignment f eatures ? dual differential 3.3v lvpecl outputs ? selectable clk, nclk or lvcmos/lvttl test_clk ? test_clk can accept the following input levels: lvcmos or lvttl ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? clk, nclk or test_clk maximum input frequency: 40mhz ? output frequency range: 25mhz to 700mhz ? vco range: 250mhz to 700mhz ? accepts any single-ended input signal on clk input with resistor bias on nclk input ? parallel interface for programming counter and output dividers ? rms period jitter: 5ps (maximum) ? cycle-to-cycle jitter: 25ps (maximum) ? 3.3v supply voltage ? -40c to 85c ambient operating temperature ? lead-free package fully rohs compliant 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 clk test_clk clk_sel v cca s_load s_data s_clock mr m5 m6 m7 m8 n0 n1 nc v ee v ee nfout0 fout0 v cco nfout1 fout1 v cc test nclk np_load vco_sel m0 m1 m2 m3 m4 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view ics8432i-101 vco_sel clk_sel test_clk clk s_load s_data s_clock np_load m0:m8 n0:n1 vco pll fout0 nfout0 fout1 nfout1 test configuration interface logic m 0 1 0 1 phase detector 1 2 4 8 mr nclk hiperclocks? ics
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 2 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer rial event occurs. as a result, the m and n bits can be hardwired to set the m divider and n output divider to a specific default state that will automatically occur during power-up. the test output is low when operating in the parallel input mode. the relationship between the vco frequency, the input frequency and the m divider is defined as follows: the m value and the required values of m0 through m8 are shown in table 3b, programmable vco frequency function table. valid m values for which the pll will achieve lock for a 25mhz reference are defined as 8 m 28. the frequency out is defined as follows: serial operation occurs when np_load is high and s_load is low. the shift register is loaded by sampling the s_data bits with the rising edge of s_clock. the contents of the shift register are loaded into the m divider and n output divider when s_load transitions from low-to-high. the m divide and n out- put divide values are latched on the high-to-low transition of s_load. if s_load is held high, data at the s_data input is passed directly to the m divider and n output divider on each rising edge of s_clock. the serial mode can be used to program the m and n bits and test bits t1 and t0. the internal reg- isters t0 and t1 determine the state of the test output as follows: time s erial l oading p arallel l oading t s t h t s t h t s m, n f unctional d escription note: the functional description that follows describes op- eration using a 25mhz clock input. valid pll loop divider val- ues for different input frequencies are defined in the input fre- quency characteristics, table 5, note 1. the ics8432i-101 features a fully integrated pll and there- fore requires no external components for setting the loop band- width. a differential clock input is used as the input to the ics8432-101. this input is fed into the phase detector. a 25mhz clock input provides a 25mhz phase detector refer- ence frequency. the vco of the pll operates over a range of 250mhz to 700mhz. the output of the m divider is also applied to the phase detector. the phase detector and the m divider force the vco output frequency to be m times the reference frequency by adjust- ing the vco control voltage. note, that for some values of m (either too high or too low), the pll will not achieve lock. the output of the vco is scaled by a divider prior to being sent to each of the lvpecl output buffers. the divider provides a 50% output duty cycle. the programmable features of the ics8432i-101 support two input modes to program the pll m divider and n output divider. the two input operational modes are parallel and serial. figure1 shows the timing diagram for each mode. in parallel mode, the np_load input is initially low. the data on inputs m0 through m8 and n0 and n1 is passed directly to the m divider and n output divider. on the low-to-high transition of the np_load input, the data is latched and the m divider remains loaded until the next low transition on np_load or until a se- fvco = f in x m t1 t0 test output 0 0 low 0 1 s_data, shift register input 1 0 output of m divider 1 1 cmos fout f igure 1. p arallel & s erial l oad o perations * note: the null timing slot must be observed. t1 t0 * null n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m0 s_clock s_data s_load np_load m0:m8, n0:n1 np_load s_load fout = fvco = f in x m nn
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 3 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 15 mt u p n ip u l l u p n o i t s i s n a r t h g i h - o t - w o l n o d e h c t a l a t a d . s t u p n i r e d i v i d m . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i d a o l _ p n f o 4 , 3 , 2 9 2 , 8 2 2 3 , 1 3 , 0 3 , 8 m , 7 m , 6 m , 1 m , 0 m 4 m , 3 m , 2 m t u p n in w o d l l u p 6 , 51 n , 0 nt u p n in w o d l l u p , c 3 e l b a t n i d e n i f e d s a e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a t n o i t c n u f 7c nd e s u n u. t c e n n o c o n 6 1 , 8v e e r e w o p. s n i p y l p p u s e v i t a g e n 9t s e tt u p t u o t u p t u o . n o i t a r e p o f o e d o m l a i r e s e h t n i e v i t c a s i h c i h w t u p t u o t s e t . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e d o m l e l l a r a p n i w o l n e v i r d 0 1v c c r e w o p. n i p y l p p u s e r o c 2 1 , 1 11 t u o f n , 1 t u o ft u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 3 1v o c c r e w o p. n i p y l p p u s t u p t u o 5 1 , 4 10 t u o f n , 0 t u o ft u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 7 1r mt u p n in w o d l l u p s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a d e t r e v n i e h t d n a w o l o g o t x t u o f s t u p t u o e u r t e h t g n i s u a c t e s e r e r a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t x t u o f n s t u p t u o d e d a o l t c e f f a t o n s e o d r m f o n o i t r e s s a . d e l b a n e e r a s t u p t u o e h t d n a . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s e u l a v t d n a , n , m 8 1k c o l c _ st u p n in w o d l l u p r e t s i g e r t f i h s e h t o t n i t u p n i a t a d _ s t a t n e s e r p a t a d l a i r e s n i s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o e g d e g n i s i r e h t n o 9 1a t a d _ st u p n in w o d l l u p e g d e g n i s i r e h t n o d e l p m a s a t a d . t u p n i l a i r e s r e t s i g e r t f i h s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o 0 2d a o l _ st u p n in w o d l l u p . s r e d i v i d e h t o t n i r e t s i g e r t f i h s m o r f a t a d f o n o i t i s n a r t s l o r t n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 2v a c c r e w o p. n i p y l p p u s g o l a n a 2 2l e s _ k l ct u p n ip u l l u p r o t u p n i k c o l c l a i t n e r e f f i d n e e w t e b s t c e l e s . t u p n i t c e l e s k c o l c , h g i h n e h w . e c r u o s e c n e r e f e r l l p e h t s a t u p n i k l c _ t s e t . t u p n i k l c _ t s e t s t c e l e s , w o l n e h w . s t u p n i k l c n , k l c s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3 2k l c _ t s e tt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c t s e t 4 2k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 5 2k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 6 2d a o l _ p nt u p n in w o d l l u p s i 0 m : 8 m t a t n e s e r p a t a d n e h w s e n i m r e t e d . t u p n i d a o l l e l l a r a p e h t s t e s 0 n : 1 n t a t n e s e r p a t a d n e h w d n a , r e d i v i d m o t n i d e d a o l . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e u l a v r e d i v i d t u p t u o n 7 2l e s _ o c vt u p n ip u l l u p . e d o m s s a p y b r o l l p n i s i r e z i s e h t n y s r e h t e h w s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t i s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 4 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 3a. p arallel and s erial m ode f unction t able t able 3b. p rogrammable vco f requency f unction t able t able 3c. p rogrammable o utput d ivider f unction t able s t u p n i s n o i t i d n o c r md a o l _ p nmnd a o l _ sk c o l c _ sa t a d _ s hx xxx x x . w o l s t u p t u o s e c r o f . t e s e r ll a t a da t a dx x x e h t o t y l t c e r i d d e s s a p s t u p n i n d n a m n o a t a d t u p t u o t s e t . r e d i v i d t u p t u o n d n a r e d i v i d m . w o l d e c r o f l a t a da t a dl x x d e d a o l s n i a m e r d n a s r e t s i g e r t u p n i o t n i d e h c t a l s i a t a d . s r u c c o t n e v e l a i r e s a l i t n u r o n o i t i s n a r t w o l t x e n l i t n u lh xxl a t a d n o a t a d h t i w d e d a o l s i r e t s i g e r t f i h s . e d o m t u p n i l a i r e s . k c o l c _ s f o e g d e g n i s i r h c a e n o a t a d _ s lh xx la t a d e h t o t d e s s a p e r a r e t s i g e r t f i h s e h t f o s t n e t n o c . r e d i v i d t u p t u o n d n a r e d i v i d m lh xx la t a d. d e h c t a l e r a s e u l a v r e d i v i d t u p t u o n d n a r e d i v i d m lh xxl x x . s r e t s i g e r t f i h s t c e f f a t o n o d s t u p n i l a i r e s r o l e l l a r a p lh xxh a t a d. d e k c o l c s i t i s a r e d i v i d m o t y l t c e r i d d e s s a p a t a d _ s w o l = l : e t o n h g i h = h e r a c t ' n o d = x n o i t i s n a r t e g d e g n i s i r = n o i t i s n a r t e g d e g n i l l a f = s t u p n i e u l a v r e d i v i d n ) z h m ( y c n e u q e r f t u p t u o 1 n0 nm u m i n i mm u m i x a m 00 1 0 5 20 0 7 01 2 5 2 10 5 3 10 4 5 . 2 65 7 1 11 8 5 2 . 1 35 . 7 8 y c n e u q e r f o c v ) z h m ( e d i v i d m 6 5 28 2 14 62 36 18421 8 m7 m6 m5 m4 m3 m2 m1 m0 m 0 5 20 1 0 0 0 0 0 10 10 5 7 21 1 00000 10 11 ? ? ????????? ? ? ????????? 0 5 66 2 0 0 0 0 1 10 10 5 7 67 2 0000 110 11 0 0 78 2 0000 11100 y c n e u q e r f t u p n i k l c _ t s e t r o t u p n i l a i t n e r e f f i d o t d n o p s e r r o c s e i c n e u q e r f g n i t l u s e r e h t d n a s e u l a v e d i v i d m e s e h t : 1 e t o n . z h m 5 2 f o
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 5 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 0 2 1a m i a c c t n e r r u c y l p p u s g o l a n a 5 1a m t able 4b. lvcmos / lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n i e g a t l o v h g i h , r m , l e s _ k l c , l e s _ o c v , a t a d _ s , d a o l _ s , d a o l _ p n , k c o l c _ s 1 n : 0 n , 8 m : 0 m 2v c c 3 . 0 +v k l c _ t s e t2v c c 3 . 0 +v v l i t u p n i e g a t l o v w o l , r m , l e s _ k l c , l e s _ o c v , a t a d _ s , d a o l _ s , d a o l _ p n , k c o l c _ s 1 n : 0 n , 8 m : 0 m 3 . 0 -8 . 0v k l c _ t s e t3 . 0 -3 . 1v i h i t u p n i t n e r r u c h g i h , r m , 1 n , 0 n , 8 m - 6 m , 4 m - 0 m , k l c _ t s e t , k c o l c _ s d a o l _ p n , d a o l _ s , a t a d _ s v c c v = n i v 5 6 4 . 3 =0 5 1a l e s _ o c v , l e s _ k l c , 5 mv c c v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , r m , 1 n , 0 n , 8 m - 6 m , 4 m - 0 m , k l c _ t s e t , k c o l c _ s d a o l _ p n , d a o l _ s , a t a d _ s v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a l e s _ o c v , l e s _ k l c , 5 m v c c , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a v h o t u p t u o e g a t l o v h g i h t s e t v c c , v 5 3 1 . 3 = i h o a m 6 3 - = 6 . 2v v l o t u p t u o e g a t l o v w o l t s e t v c c , v 5 3 1 . 3 = i l o a m 6 3 = 5 . 0v a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 6 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 5. i nput f requency c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c t able 6. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i 1 e t o n ; k l c _ t s e t4 15 2z h m 1 e t o n ; k l c n , k l c4 15 2z h m k c o l c _ s 5 2z h m n i h t i w e t a r e p o o t o c v e h t r o f t e s e b t s u m e u l a v m e h t , e g n a r y c n e u q e r f k l c _ t s e t d n a t u p n i l a i t n e r e f f i d e h t r o f : 1 e t o n 8 1 e r a m f o s e u l a v d i l a v , z h m 4 1 f o y c n e u q e r f t u p n i m u m i n i m e h t g n i s u . e g n a r z h m 0 0 7 o t z h m 0 5 2 e h t m . 0 5 0 1 e r a m f o s e u l a v d i l a v , z h m 5 2 f o y c n e u q e r f m u m i x a m e h t g n i s u m . 8 2 t able 4d. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - t able 4c. d ifferential dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l cv c c v = n i v 5 6 4 . 3 =0 5 1a k l c nv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i k l cv c c v , v 5 6 4 . 3 = n i v 0 =5 -a k l c nv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p5 1 . 03 . 1v v r m c e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n c c . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o5 2 . 1 30 0 7z h m t ) c c ( t i j3 , 1 e t o n ; r e t t i j e l c y c - o t - e l c y cz h m 0 5 3 > o c v f5 2s p t ) r e p ( t i j1 e t o n ; s m r , r e t t i j d o i r e pz h m 0 0 1 > t u o f5s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 5 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p t s e m i t p u t e s d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n t h e m i t d l o h d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n c d oe l c y c y t u d t u p t u o1 > n7 43 5% t w p h t d i w e s l u p t u p t u o1 = nt pd o i r e 0 5 1 - 2 /t pd o i r e 0 5 1 + 2 /s p t k c o l e m i t k c o l l l p 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . s t u p n i l a t x g n i s u e c n a m r o f r e p r e t t i j : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 7 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer p arameter m easurement i nformation 3.3v o utput l oad ac t est c ircuit d ifferential i nput l evel c ycle - to -c ycle j itter p eriod j itter o utput d uty c ycle /p ulse w idth /p eriod o utput s kew o utput r ise /f all t ime v cmr cross points v pp v ee nclk v cc clk scope qx nqx lvpecl 2v -1.3v 0.165v v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram t sk(o) nfoutx foutx nfouty fouty clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% foutx nfoutx ? ? ? ? nfoutx foutx t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 v cc , v cca , v cco v ee
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 8 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer s torage a rea n etworks a variety of technologies are used for interconnection of the elements within a san. the tables below list the common appli- table 7. common sans application frequencies table 8. configuration details for sans applications a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics8432i-101 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 2. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc y g o l o n h c e t t c e n n o c r e t n ie t a r k c o l c s e d r e s o t y c n e u q e r f e c n e r e f e r ) z h m ( y c n e u q e r f l a t s y r c ) z h m ( t e n r e h t e t i b a g i gz h g 5 2 . 15 2 . 6 5 1 , 0 5 2 , 5 2 15 2 1 3 5 . 9 1 , 5 2 l e n n a h c e r b i f z h g 5 2 6 0 . 1 1 c f z h g 0 5 2 1 . 2 2 c f 5 2 1 8 . 2 3 1 , 5 2 1 . 3 5 , 5 2 . 6 0 15 2 , 5 2 6 5 1 0 6 . 6 1 d n a b i n i f n iz h g 5 . 20 5 2 , 5 2 15 2 cation frequencies as well as the ics8432i-101 configurations used to generate the appropriate frequency. t c e n n o c r e t n i y g o l o n h c e t t u p n i k l c n , k l c ) z h m ( 1 0 1 - i 2 3 4 8 s c i y c n e u q e r f t u p t u o s e d r e s o t ) z h m ( 1 0 1 - i 2 3 4 8 s c i s g n i t t e s n & m 8 m7 m6 m5 m4 m3 m2 m1 m0 m1 n0 n t e n r e h t e t i b a g i g 5 25 2 1 0000 10 100 10 5 20 5 2 0000 10 1000 1 5 25 2 . 6 5 1 0000 1100 110 5 2 1 3 5 . 9 15 2 . 6 5 1 000 100000 10 1 l e n n a h c r e b i f 5 25 2 1 . 3 5 0000 1000 111 5 25 2 . 6 0 1 0000 1000 110 2 l e n n a h c r e b i f5 2 6 5 1 0 6 . 6 15 2 1 8 . 2 3 1 000 100000 10 d n a b i n i f n i 5 25 2 1 0000 10 100 10 5 20 5 2 0000 10 1000 1
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 9 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, termi- nating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be rec- ommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs figure 3 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 3. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 10 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer f igure 5c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 5b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 5d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5d show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 5a. h i p er c lock s clk/ n clk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 5a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 11 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer l ayout g uideline the schematic of the ics8432i-101 layout example used in this layout guideline is shown in figure 6a. the ics8432i-101 recommended pcb board layout for this example is shown in figure 6b . this layout example is used as a general guideline. f igure 6a. s chematic of r ecommended l ayout c16 10u termination a u1 8432-101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 m5 m6 m7 m8 n0 n1 nc vee test vdd fout1/2 nfout1/2 vcco fout nfout vee mr s_clock s_data s_load vdda nclk_sel ref_in clk m4 m3 m2 m1 m0 vco_sel np_load nclk r1 125 vcca tl2 zo = 50 ohm test in- in- vcc s_clock vcc r3 125 c11 0.01u xtal_sel r3 50 s_load r7 10 tl1 zo = 50 ohm mr in+ r4 84 fout r2 84 s_data r1 50 c15 0.1u nclk clk vcc in+ termination b (not shown in the layout) foutn r2 50 c14 0.1u vcc the layout in the actual system will depend on the selected com- ponent types, the density of the components, the density of the traces, and the stack up of the p.c. board.
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 12 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer gnd close to the input pins of the receiver u1 r3 vcca tl1 c14 pin 1 tl1n tl1 vcc r4 c11 c16 c15 tl1, tl2 are 50 ohm traces and equal length r1 tl1n r7 via r2 the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors c14 and c15 as close as pos- sible to the power pins. if space allows, placing the decoupling capacitor at the component side is preferred. this can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. maximize the pad size of the power (ground) at the decoupling capacitor. maximize the number of vias between power (ground) and the pads. this can reduce the inductance between the power (ground) plane and the component power (ground) pins. if v cca shares the same power supply with v cc , insert the rc filter r7, c11, and c16 in between. place this rc filter as close to the v cca as possible. c lock t races and t ermination the component placements, locations and orientations should be arranged to achieve the best clock signal quality. poor clock signal quality can degrade the system performance or cause system fail- ure. in the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. any ring- ing on the rising or falling edge or excessive ring back can cause system failure. the trace shape and the trace delay might be re- stricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the traces with 50 transmission lines tl1 and tl2 at fout and nfout should have equal delay and run ad- jacent to each other. avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock trace on same layer. whenever possible, avoid any vias on the clock traces. any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. ? make sure no other signal trace is routed between the clock trace pair. the matching termination resistors r1, r2, r3 and r4 should be located as close to the receiver input pins as possible. other termination schemes can also be used but are not shown in this example. f igure 6b. pcb b oard l ayout for ics8432i-101
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 13 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics8432i-101. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8432i-101 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 120ma = 416mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power _max (3.465v, with all outputs switching) = 416mw + 60mw = 476mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 9 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.476w * 42.1c/w = 105c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67. 8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47. 9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 9. t hermal r esistance ja for 32- pin lqfp, f orced c onvection
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 14 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 7. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 15 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer r eliability i nformation t ransistor c ount the transistor count for ics8432i-101 is: 3712 t able 10. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67. 8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47. 9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 16 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer p ackage o utline - y s uffix for 32 l ead lqfp n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 6 . 1 1 a 5 0 . 05 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 00 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 7 c c c 0 1 . 0 t able 11. p ackage d imensions reference document: jedec publication 95, ms-026
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 17 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 12. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other ext raordinary envir onmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 1 - i y d 2 3 4 8 s c i1 0 1 - i d 2 3 4 8 s c ip f q l d a e l 2 30 5 2c 5 8 o t c 0 4 - t 1 0 1 - i y d 2 3 4 8 s c i1 0 1 - i d 2 3 4 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l 1 0 1 - i y d 2 3 4 8 s c il 1 0 1 i d 2 3 4 s c ip f q l " e e r f - d a e l " d a e l 2 30 5 2c 5 8 o t c 0 4 - t f l 1 0 1 - i y d 2 3 4 8 s c il 1 0 1 i d 2 3 4 s c ip f q l " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries.
8432dyi-101 www.icst.com/products/hiperclocks.html rev. a may 23, 2005 18 integrated circuit systems, inc. ics8432i-101 700mh z , d ifferential - to -3.3v lvpecl f requency s ynthesizer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 2 1 t 1 7 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f . s t r a p e e r f - d a e l d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 3 2 / 5

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